In the process of reading digital data from a digital recording device, the bit error rate changes with the phase relationship of the digital data signal and the synchronization signal. Therefore, in digital recording devices, it is necessary to measure the changes in bit error rate with changes in the phase of the synchronization signal and to investigate the allowable range of phase difference and jitter of the synchronization signal.
This invention is used especially in the measurement of bit errors of digital signals which are read from digital recording devices, etc. Moreover, by means of this invention, which can vary the phase of the synchronization signal arbitrarily, it is possible to optimize the phase of a synchronization signal so that bit errors which occur during read-out of a digital recording device are minimized.
Hereafter, an example will be discussed of a change in the bit error rate due to changes in the phase of the synchronization signal, by using FIGS. 6a-6e and 7a-7e. The signal F is the original digital signal comprising information which has been recorded by a recording device; the signal read out by the digital recording device is ordinarily in a distorted waveform, as shown by waveform A (FIG. 6b). B is the synchronization signal (FIG. 6c). The small vertical lines shown in signal waveform F are not signals, but signs which show the synchronization positions. Moreover, the dots shown in Signal A are signs which show the sampling positions, as discussed below.
In FIGS. 6a-6e, there is no phase difference between original digital signal F, i.e., read-out signal A, and synchronization signal B. Therefore, if signal A is sampled at the rising edge of synchronization signal B, the correct value of signal A is sampled and a discrete signal G is obtained (the dots in FIG. 6d). This signal G is converted to binary digits by a threshold value J, shown by the horizontal dotted line in FIG. 6d, and digital signal H (FIG. 6e) is obtained. Signal H includes no errors and is similar to original digital signal F.
However, if as shown in FIGS. 7a-7e, there is a large phase difference between read-out signal A and synchronization signal B, the timing of the sampling during data reproduction is displaced from the original timing, and correct values are not sampled. As a result, when sampled signal G is converted to binary digits by threshold value J, sample K gives rise to a bit error and reproduced signal H contains an error. In FIGS. 7a-7e, even if no errors arise, the margin between the samples with values near the threshold and noise, in an actual circuit, are small, and the probability of bit errors arising is high.
As discussed above, the bit error rate changes with the displacement of the sample timing, due to the phase difference of the synchronization signal. In order to measure the changes in the bit error rate with respect to changes in the phase of the synchronization signal, it must be possible to generate a synchronization signal from the input digital signal and to set the phase of the synchronization signal arbitrarily.
In generating a synchronization signal from an input signal, a second order phase locked loop is generally used, such as shown in FIG. 8. In the phase locked loop, the output of a voltage-controlled oscillator 8 is synchronization signal B. Input signal A and synchronization signal B are compared by a phase detector 19, and a current E, corresponding to the phase difference of the two signals, is output from phase detector 19. Current E and an offset current L (with a constant magnitude) from a direct current source 20 are combined by current-joining means 21 and input into an integrator 7. The current is integrated in integrator 7 and fed back to the input of voltage-controlled oscillator 8, completing the feed-back loop.
Due to the negative feed-back of the loop, the oscillation frequency and phase of voltage-controlled oscillator 8 finally settle and become constant; and input signal A and synchronization signal B are phase-locked with a certain phase difference. Since the control voltage of voltage-controlled oscillator 8, i.e., the output voltage of integrator 7, is held constant by feed-back in the state in which the phases are locked, the input of integrator 7 is held at zero. That is, the phases are locked in a state in which the output current of phase detector 19 and the offset current L cancel each other.
When offset current L from direct current source 20 is changed to a new value, the feed-back of the loop acts in the direction to make the input of integrator 7 zero; hence, the output of phase detector 19 changes in such a way that the new value of offset current L is canceled out, and the loop locks to the new phase. Therefore, by controlling the magnitude of direct current L, it is possible to change the phase difference of input signal A and synchronization signal B to any arbitrary value. The conventional phase locked loop controls the phase of the synchronization signal to any arbitrary value by this kind of method.
This method presupposes that input signal A is a repetitive waveform, i.e., the edge of the input signal A comes in a regular manner. In cases of input signals with edges which occur intermittently, like digital signals, this method does not operate well. The reasons for this will be discussed below, by means of examples shown in FIGS. 9 and 10. Furthermore, in the diagrams in which a digital input signal A, discussed below, is shown, the waveform is not drawn in a distorted manner, as in FIG. 6, for purposes of simplification.
Output signal E of phase detector 19, in FIGS. 9 and 10, consists of pulses with widths which extend from the rising or falling edge of digital input signal A to the rising edge of synchronization signal B. The feedback acts in such a way that a phase difference arises by which the mean value of signal E and the offset current L cancel each other. That is, the phase difference becomes such that the areas shown by the diagonal hatching in the figure become equal.
FIG. 9 is an example in which the rising or falling edges of digital signal A alternatively come once each period of the synchronization signal. In FIG. 10, on the other hand, an example is shown in which the rising or falling edges of the digital signal alternatively come once in two periods of the synchronization signal. Comparing the outputs E of phase detector 19, the widths of the pulses in FIGS. 9 and 10 are the same, but the numbers of pulses are in the ratio of 1 to 2. Therefore, the mean current of E in FIG. 10 is 1/2 that of FIG. 9. In order to control the phase difference so that it is the same as in FIG. 9, the direct current offset current L of FIG. 10 must be made 1/2. In FIG. 10, the current L is drawn as 1/2. Conversely, if the magnitude of the offset current L is not changed, the feedback acts in a direction such that the pulse width of E broadens so that a phase difference is caused which cancels this, and the phase difference doubles between the digital signal and the synchronization signal.
Thus, the output E of phase detector 19 appears only when an edge of the input signal occurs, so that, in the case of an input signal the edges of which come intermittently, output E of phase detector 19 varies with the frequency of the edges, even though the phase difference does not vary. Therefore, in a case in which the offset current is constant, the phase difference varies in the opposite manner.
In the case of a digital signal input, the frequency with which the edges of input signal A occur is completely random; therefore, even if the magnitude of offset current L is constant, the phase of synchronization signal B varies randomly and cannot be kept a constant value.
In the case of an input signal, the edges of which come intermittently, such as a digital signal, the phase locked loop is settled in a stable manner and a synchronization signal with a constant phase is obtained only when the offset current L is zero. That occurs when the edges of input signal A and the edges of synchronization signal B coincide with each other. The output E of the phase detector 19 is also always zero.
Thus, in the means of FIG. 8, the phase of the synchronization signal cannot be changed to an arbitrary value with respect to input signals, the edges of which come intermittently, such as digital signals.
Therefore, as a means for generating a synchronization signal which has a phase difference with respect to an input signal, the edges of which come intermittently, a method which uses a phase locked loop and a delay circuit, as shown in FIG. 11, has been proposed. Phase locked loop 22 of FIG. 11 is a phase locked loop of the kind shown in FIG. 8 above; it holds at zero the phase difference between the input signal and the synchronization signal. If its output is output through the delay circuit 23 as synchronization signal B, synchronization signal B is delayed by a quantity which is determined by the characteristic of delay circuit 23 with respect to the output of phase locked loop 22. Therefore, a synchronization signal B can be obtained which has a constant, arbitrarily chosen phase difference from input signal A. However, this phase difference is a constant, corresponding to the characteristic of delay circuit 23; it is not possible to make it variable. Conversely, in order to make the phase variable, a delay circuit with a variable delay time is needed, which is hard to realize in practice.
As a means for outputting a synchronization signal with a variable phase with respect to input signals with intermittent edges, such as digital data, there is a method which uses a phase locked loop with a frequency divider, as shown in FIG. 12.
In FIG. 12, divider 24 divides the output of voltage-controlled oscillator 8 into n parts, and n signals are output, each of which has a phase which differs by 360/n degrees from the previous one. If one specific signal among these n signals is returned to phase detector 19, the signal is phase-locked, with a phase difference of zero with respect to input signal A. Therefore, in the phase-locked state, the frequency of the signal is maintained so that it is equal to that of input signal A, and the phase difference becomes zero; hence, the output of the voltage-controlled oscillator 8 is a frequency n times that of input signal A, and it becomes a signal which is synchronized with the input signal. The output of divider 24, which divides by n, is equal to the frequency of the input signal A, and becomes n signals, such that their phase differences are integral multiples of 360/n degrees.
By selecting a suitable signal from these n signals by means of selection switch 25, a signal can be obtained which is synchronized with the input signal A and the phase of which is an integral multiple of 360/n degrees, and is output as the synchronization signal. For example, if n is 8, synchronization signals with phases which can be varied by intervals of 360/8=45 degrees can be generated.
Since the steps by which the phase is varied are limited to 360/n degrees, it is necessary to make the division ratio n of the divider large when one wishes to vary the phase very precisely. If the division ratio n becomes large, divider 24 and selection switch 25 become complex. Moreover, if the division ratio n is made large, the frequencies handled by voltage-controlled oscillator 8 and divider 24 also become high, which leads to technical difficulties. Moreover, even if the division ratio n can be made large, the phase of the synchronization signal can only be varied in steps, and not continuously.
The prior art thus made it possible to vary the phase of a synchronization signal to arbitrary values, in cases in which the input signals were repeated waveforms. But the phase of a synchronization signal with respect to an input signal, in cases of signals with edges which come intermittently, such as digital signals, was either constant at a specific value, or even if it was variable, it could only be varied in certain steps, and could not be varied continuously to any arbitrary phase.
This invention has the purpose of solving the aforementioned problems by providing a synchronization signal generating device which has a means by which the phase difference of the synchronization signal can be varied arbitrarily and continuously, even with respect to input signals with intermittent edges.